---
id: CVE-2026-45894
title: 'iommu/vt-d: Clear Present bit before tearing down PASID entry'
summary: |-
  In the Linux kernel, the following vulnerability has been resolved:

  iommu/vt-d: Clear Present bit before tearing down PASID entry

  The Intel VT-d Scalable Mode PASID table entry consists of 512 bits (64
  bytes). When tearing down an entr…
severity: high
cvss: 7.8
cvssVector: 'CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:H/A:H'
cvssSource: cna
vendor: Linux
product: Linux
affected:
  - >-
    Linux >= 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 <
    a84d30e8d2bacd21782a6481158b7c9c552f4868
  - >-
    Linux >= 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 <
    821807c167b7b48a41b95b6607c6b9f97600f7d9
  - >-
    Linux >= 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 <
    949d71666e9dd19f21e7b4b53a88cd2c5b902858
  - >-
    Linux >= 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 <
    75ed00055c059dedc47b5daaaa2f8a7a019138ff
  - Linux 5.0
ssvc:
  exploitation: none
  automatable: 'no'
  technicalImpact: total
  timestamp: '2026-10-16T15:18:18.601653Z'
published: '2026-05-27'
updated: '2026-10-16'
sourceUpdated: '2026-10-16T15:20:46.382Z'
source: CVEORG
sourceUrl: 'https://www.cve.org/CVERecord?id=CVE-2026-45894'
references:
  - url: 'https://git.kernel.org/stable/c/a84d30e8d2bacd21782a6481158b7c9c552f4868'
  - url: 'https://git.kernel.org/stable/c/821807c167b7b48a41b95b6607c6b9f97600f7d9'
  - url: 'https://git.kernel.org/stable/c/949d71666e9dd19f21e7b4b53a88cd2c5b902858'
  - url: 'https://git.kernel.org/stable/c/75ed00055c059dedc47b5daaaa2f8a7a019138ff'
tags:
  - cve.org
epss: 0.00149
epssPercentile: 0.03704
ingestedAt: '2026-10-16T17:24:46.700Z'
---

## Overview

In the Linux kernel, the following vulnerability has been resolved:

iommu/vt-d: Clear Present bit before tearing down PASID entry

The Intel VT-d Scalable Mode PASID table entry consists of 512 bits (64
bytes). When tearing down an entry, the current implementation zeros the
entire 64-byte structure immediately using multiple 64-bit writes.

Since the IOMMU hardware may fetch these 64 bytes using multiple
internal transactions (e.g., four 128-bit bursts), updating or zeroing
the entire entry while it is active (P=1) risks a "torn" read. If a
hardware fetch occurs simultaneously with the CPU zeroing the entry, the
hardware could observe an inconsistent state, leading to unpredictable
behavior or spurious faults.

Follow the "Guidance to Software for Invalidations" in the VT-d spec
(Section 6.5.3.3) by implementing the recommended ownership handshake:

1. Clear only the 'Present' (P) bit of the PASID entry.
2. Use a dma_wmb() to ensure the cleared bit is visible to hardware
   before proceeding.
3. Execute the required invalidation sequence (PASID cache, IOTLB, and
   Device-TLB flush) to ensure the hardware has released all cached
   references.
4. Only after the flushes are complete, zero out the remaining fields
   of the PASID entry.

Also, add a dma_wmb() in pasid_set_present() to ensure that all other
fields of the PASID entry are visible to the hardware before the Present
bit is set.

## Affected

- `Linux >= 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 < a84d30e8d2bacd21782a6481158b7c9c552f4868`
- `Linux >= 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 < 821807c167b7b48a41b95b6607c6b9f97600f7d9`
- `Linux >= 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 < 949d71666e9dd19f21e7b4b53a88cd2c5b902858`
- `Linux >= 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 < 75ed00055c059dedc47b5daaaa2f8a7a019138ff`
- `Linux 5.0`

## Remediation

Refer to the linked advisories for vendor-supplied fixes and affected version ranges.